Date: Thu, 21 Nov 1996 20:26:45 GMT
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 <b> Jean-Loup Baer</b>, Professor
and Adjunct Professor of Electrical Engineering,
received the Diplome d'Ing&#233;nieur in Electrical
Enginering and the Doctorat 3e cycle in Computer Science from the
Universit&#233; de Grenoble (France) and the Ph.D. from UCLA in 1968.
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Prior to joining the University of Washington in 1969,
he was a Research Engineer with the Laboratoire de
Calcul, Universit&#233; de Grenoble, and a member of the Digital Technology
Group at UCLA (1966-69). His present interests are in parallel and
distributed processing and  computer systems architecture. 
He is author or coauthor of more than 60 papers in these
areas and the author of the textbook ``Computer Systems Architecture''
(Computer Science Press, 1980).
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Professor Baer has served as an IEEE Computer Science Distinguished
Visitor, and was an ACM National Lecturer.  He is a Guggenheim Fellow,
an IEEE Fellow,
an editor of the <em> Journal of Parallel and Distributed Computing</em>,
and of the <em> Journal of Computer Languages</em>.  He has served as
Program Chairman for the 1977 International Conference on Parallel
Processing, as co-Program Chairman for the 10th International
Symposium on Computer Architecture, and as General co-Chairman of
the 17th International
Symposium on Computer Architecture. He is currently Chair of ACM SIGARCH.
Eighteen  Ph.D. students have completed their dissertation under Professor
Baer's direction. Twelve of them work in industry or research laboratories
and six are in
academia.
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Although he has been in the U.S.A. for over 30 years, Dr. Baer has
had no difficulty in retaining his French accent.
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<h3> Courses  </h3>
<ul>
        <li> <!WA0><!WA0><!WA0><a href = "http://www.cs.washington.edu/education/courses/378/CurrentQtr">CSE 378</a>
        <li> <!WA1><!WA1><!WA1><a href = "http://www.cs.washington.edu/education/courses/590g/">CSE 590g</a>
  
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<h3> Recent research projects </h3>
<ul>
        <li> Look under the <!WA2><!WA2><!WA2><a href = http://www.cs.washington.edu/research/arch/>Computer architecture</a> page. Projects in which I am/was involved are:
<ul>
        <li> Cache coherence protocols for <!WA3><!WA3><!WA3><a href = http://www.cs.washington.edu/research/arch/hier-cache-coh.html>cluster architectures</a> and improved protocols for <!WA4><!WA4><!WA4><a href="http://www.cs.washington.edu/homes/baer/hpca95.ps">single bus </a> systems.
         <li> Use and performance of <!WA5><!WA5><!WA5><a href="http://www.cs.washington.edu/homes/xqin/hpca3.ps"> software primitives</a> for clusters (to appear in HPCA-3)
	<li> Prefetching in uniprocessors, via <!WA6><!WA6><!WA6><a href = http://www.cs.washington.edu/research/arch/data-pre-hp.html> hardware </a>  (see also IEEE TC May 95)and comparison
with <!WA7><!WA7><!WA7><a href = http://www.cs.washington.edu/research/arch/latency-nb-pre.html>
non-blocking caches </a> (see also ASPLOS-V); prefetching in multiprocessors
(cf. ISCA 94)
	<li> Impact of speculative execution on I-caches , see 
<!WA8><!WA8><!WA8><a href = http://www.cs.washington.edu/homes/dlee/> Dennis Lee</a> home page and
ISCA 95.
	<li> Parallel trace-driven simulations: <!WA9><!WA9><!WA9><a href = http://www.cs.washington.edu/research/arch/sim-par-ip.html>conservative approach</a> (see  also ICPP 95);
<!WA10><!WA10><!WA10><a href = http://www.cs.washington.edu/research/arch/sim-opt.html> optimistic
approach</a> and their <!WA11><!WA11><!WA11><a href = ttp://www.cs.washington.edu/research/arch/sim-cons-opt.html> comparison</a> (see also Distributed Simulation 95)

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